The present invention relates to a semiconductor integrated circuit device including one or more memory macros and a self-testing block for testing the one or more memory macros.
As the integration levels and functionality in system LSIs have been increased, the capacity of incorporated memories has been continuously increasing year after year and built-in self-test (BIST) technique, as the means for testing these memories, has been growing in importance. BISA (built-in self-analyzer), BISR (built-in self-repair) and the like are also known as techniques for realizing a higher level of self-testing.
In recent years, it has also been required to efficiently perform wafer level burn-in (WLBI) tests, reliability tests, failure analysis, and the like.
According to the technique in U.S. Pat. No. 6,907,555, a self test is conducted by using a relatively small number of input/output terminals, which is desirable particularly when a WLBI test is performed.
Examples of a reliability test, such as test and analysis and life test, of a semiconductor integrated circuit device include various kinds of tests and analyses ranging from defective/non-defective selection to a continuous accelerated operation test, such as a WLBI test, performed for a specified length of time, specification analysis of malfunctioning part, detailed analysis of unstable operation, analysis of an abnormal condition occurring in standby current, and the like. And it is difficult to perform these tests and analyses with the maximum efficiency.